DFFT : Design For Functional Testability
نویسندگان
چکیده
Creating functional tests that work on an ATE has always been a significant challenge [1]. This paper identifies the fundamental mechanisms for functional test failures of an SOC on an ATE. Taking these mechanisms into account during the design process of a chip can substantially reduce the efforts needed to make functional tests work. We call this process design for functional testability (DFFT).
منابع مشابه
Early Prediction of Testability by Analyzing Behavioral VHDL Specifications
A behavioral testability analysis technique is proposed for early prediction of testability by analyzing behavioral specifications written in VHDL. The technique extracts functional properties by an analysis of variable range, statement hardness and dependency relation between variables of the specification. It predicts the testability for the whole design with a low computational cost. Another...
متن کاملDesigning of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1
Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...
متن کاملTestability Measurement Model for Object Oriented Design (TMMOOD)
Measuring testability early in the development life cycle especially at design phase is a criterion of crucial importance to software designers, developers, quality controllers and practitioners. However, most of the mechanism available for testability measurement may be used in the later phases of development life cycle. Early estimation of testability, absolutely at design phase helps designe...
متن کاملTwo-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues
New Design for Testability techniques aimed both at overcoming the problem of testing array architectures composed of sequential cells and guaranteeing fault tolerance through reconfiguration are proposed. Two strategies have been envisioned: (1) structural DfT techniques whose goal is to modify the interconnecting network embedding each cell, and (2) functional techniques aimed at defining a t...
متن کاملTestabiiity of Convergent Tree Circuits - Computers, IEEE Transactions on
The testing properties of a class of regular circuits called convergent trees are investigated. Convergent trees include such practical circuits as comparators, multiplexers, and carry-lookahead adders. The conditions for the testability of these tree circuits are derived for a functional fault model. The notion of L-testability is introduced, where the number of tests for a plevel tree is dire...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003